Devices incorporating integrated dectors and ultra-small vertical cavity surface emitting laser emitters

ABSTRACT

A semiconductor device includes a detector structure. The detector structure includes an integrated circuit on a substrate, and a photo detector on an upper surface of the integrated circuit that is opposite the substrate, where the substrate is non-native to the photo detector. A System-on-Chip apparatus includes at least one laser emitter on a non-native substrate, at least one photo detector on the non-native substrate, and an input/output circuit. The at least one photo detector of the second plurality of photo detectors is disposed on an integrated circuit between the at least one photo detector and the non-native substrate to form a detector structure.

CLAIM OF PRIORITY

This application is a continuation of and claims priority from U.S.application Ser. No. 15/951,884, filed Apr. 12, 2018, which claimspriority from U.S. Provisional Patent Application No. 62/484,701entitled “LIGHT DETECTION AND RANGING (LIDAR) DEVICES AND METHODS OFFABRICATING THE SAME” filed Apr. 12, 2017, and U.S. Provisional PatentApplication No. 62/613,985 entitled “ULTRA-SMALL VERTICAL CAVITY SURFACEEMITTING LASER (VCSEL) AND ARRAYS INCORPORATING THE SAME” filed Jan. 5,2018, with the United States Patent and Trademark Office, thedisclosures of which are incorporated by reference herein.

FIELD

The present invention relates to semiconductor-based lasers and relateddevices and methods of operation.

BACKGROUND

Many emerging technologies, such as Internet-of-Things (IoT) andautonomous navigation, may involve detection and measurement of distanceto objects in three-dimensional (3D) space. For example, automobilesthat are capable of autonomous driving may require 3D detection andrecognition for basic operation, as well as to meet safety requirements.3D detection and recognition may also be needed for indoor navigation,for example, by industrial or household robots or toys.

Light based 3D measurements may be superior to radar (low angularaccuracy, bulky) or ultra-sound (very low accuracy) in some instances.For example, a light-based 3D sensor system may include a detector (suchas a photodiode or camera) and a light emitting device (such as a lightemitting diode (LED) or laser diode) as light source, which typicallyemits light outside of the visible wavelength range. A vertical cavitysurface emitting laser (VCSEL) is one type of light emitting device thatmay be used in light-based sensors for measurement of distance andvelocity in 3D space.

SUMMARY

Some embodiments described herein are directed to a laser diode, such asa VCSEL or other surface-emitting laser diode, an edge-emitting laserdiode, and/or other semiconductor laser, and arrays incorporating thesame.

According to some embodiments, a semiconductor device includes adetector structure. The detector structure includes an integratedcircuit on a substrate, and a photo detector on an upper surface of theintegrated circuit that is opposite the substrate, where the substrateis non-native to the photo detector.

In some embodiments, a ratio of a first area of the photo detector to asecond area of the detector structure is greater than 80%.

In some embodiments, the semiconductor device further includes aplurality of laser emitters on the substrate. The substrate isnon-native to the plurality of laser emitters and a spacing betweenadjacent ones of the laser emitters is less than 500 μm.

In some embodiments, the plurality of laser emitters and the detectorstructure are disposed on opposite sides of the substrate.

In some embodiments, the plurality of laser emitters are configured toemit light through the substrate.

In some embodiments, the photo detector comprises a plurality of photodetectors, and a spacing between adjacent photo detectors of theplurality of photo detectors is less than 20 μm.

In some embodiments, the plurality of photo detectors comprises a firstarray of photo detectors having a first density and a second array ofphoto detectors having a second density, different from the firstdensity.

In some embodiments, the photo detector comprises a broken tetherportion and/or a relief feature at a periphery thereof.

In some embodiments, the semiconductor device further includes a lensleton the photo detector.

According to some embodiments, a method of fabricating a semiconductordevice includes disposing a detector structure on a substrate, where thedetector structure includes an integrated circuit on a substrate, and aphoto detector on a surface of the integrated circuit that is oppositethe substrate. The substrate is non-native to the photo detector.

In some embodiments of the method, a ratio of a first area of the photodetector to a second area of the detector structure is greater than 80%.

In some embodiments of the method, the photo detector is disposed on theupper surface of the integrated circuit using a micro-transfer printingprocess.

In some embodiments of the method, the micro-transfer printing processresults in the formation of a broken tether portion and/or a relieffeature at a periphery of the of photo detector.

In some embodiments, the method further includes disposing a pluralityof laser emitters on the substrate using the micro-transfer printingprocess, wherein the substrate is non-native to the plurality of laseremitters.

In some embodiments of the method, the micro-transfer printing processresults in a formation of a broken tether portion and/or a relieffeature at a periphery of at least one of the plurality of laseremitters.

In some embodiments of the method, the plurality of laser emitters andthe detector structure are disposed on opposite sides of the substrate.

According to some embodiments, a System-on-Chip apparatus includes atleast one laser emitter on a non-native substrate, at least one photodetector on the non-native substrate, and an input/output circuit. Theat least one photo detector is disposed on an integrated circuit betweenthe at least one photo detector and the non-native substrate to form adetector structure.

In some embodiments, a ratio of a first area of the at least one photodetector to a second area of the detector structure is greater than 80%.

In some embodiments, the System-on-Chip apparatus further includes atiming control processor coupled to the at least one laser emitter, theat least one photo detector, and the input/output circuit.

In some embodiments, a surface of the non-native substrate having the atleast one laser emitter and the at least one photo detector thereon hasa width and/or a length of less than 2 millimeters.

Other devices, apparatus, and/or methods according to some embodimentswill become apparent to one with skill in the art upon review of thefollowing drawings and detailed description. It is intended that allsuch additional embodiments, in addition to any and all combinations ofthe above embodiments, be included within this description, be withinthe scope of the invention, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example light-based 3D sensor systemin accordance with some embodiments described herein.

FIG. 2A is a plan view illustrating an example laser diode with reducedanode and cathode contact dimensions in accordance with some embodimentsdescribed herein.

FIG. 2B is a cross-sectional view of the laser diode of FIG. 2A.

FIG. 2C is a perspective view illustrating an example laser diode inaccordance with some embodiments described herein in comparison to aconventional VCSEL chip.

FIG. 3A is a perspective view illustrating a distributed emitter arrayincluding laser diodes in accordance with some embodiments describedherein.

FIG. 3B is a perspective view illustrating a distributed emitter arrayincluding laser diodes on a curved substrate in accordance with someembodiments described herein.

FIGS. 4A-4F are perspective views illustrating an example fabricationprocess for laser diodes in accordance with some embodiments describedherein.

FIGS. 4A′-4G′ are cross-sectional views illustrating an examplefabrication process for laser diodes in accordance with some embodimentsdescribed herein.

FIGS. 5A, 5B, and 5C are images of VCSEL arrays assembled in accordancewith some embodiments described herein.

FIGS. 5D and 5E are magnified images illustrating residual tetherportions and relief features of VCSELs in accordance with someembodiments described herein.

FIG. 6A is a perspective view illustrating an example emitter arrayincluding heterogeneous integration of distributed laser diodes anddistributed driver transistors in accordance with some embodimentsdescribed herein.

FIG. 6B is schematic view illustrating an equivalent circuit diagram forthe distributed emitter array of FIG. 6A.

FIG. 6C is a cross-sectional view of the distributed emitter array takenalong line 6C-6C′ of FIG. 6A.

FIG. 6D is a schematic view illustrating an alternate equivalent circuitdiagram for the distributed emitter array of FIG. 6A.

FIG. 7A is a perspective view illustrating an example LIDAR device inaccordance with some embodiments described herein.

FIG. 7B is an exploded view illustrating example components of the LIDARdevice of FIG. 7A.

FIG. 7C is a perspective view illustrating another example LIDAR devicein accordance with some embodiments described herein.

FIG. 8 is a block diagram illustrating an example system architecturefor a LIDAR device in accordance with some embodiments described herein.

FIG. 9 is a cross-sectional view illustrating an example laser diodearray in accordance with further embodiments described herein.

FIGS. 10A and 10B are cross-sectional views of examples of a detectorhaving reduced dimensions in accordance with some embodiments describedherein.

FIG. 11A illustrates an example of a conventional detector array.

FIG. 11B illustrates an example of a detector array and individualdetector, according to some embodiments described herein.

FIG. 11C illustrates a schematic representation of a distributed arrayof detectors printed on a non-native substrate, according to someembodiments described herein.

FIG. 12A illustrates a schematic representation of a combination ofemitters and detectors heterogeneously integrated on a non-nativesubstrate, according to some embodiments described herein.

FIGS. 12B and 12C illustrate example configurations in which arrays ofVCSELs and detectors are variously arranged, according to someembodiments described herein.

FIGS. 13A and 13B illustrate examples of heterogeneous configurations ofVCSELs and detectors on a non-native substrate, according to someembodiments described herein.

FIGS. 14A, 14B, 14C, and 14D illustrate arrays in which emitters anddetectors of different wavelengths may be combined in heterogeneousarrays, according to some embodiments described herein.

FIGS. 15A, 15B, and 15C illustrate examples of configurations ofdetectors that provide a wider field of view, according to someembodiments described herein.

FIGS. 16A and 16B illustrate an integrated system-on-chip (SoC)incorporating the heterogeneous array of emitters and detectors,according to some embodiments described herein.

DETAILED DESCRIPTION

Embodiments described herein may arise from realization that morecompact arrays of light emitters may be advantageous in emergingtechnologies. For example, as shown in FIG. 1, a light-based 3D sensorsystem 100, such as a Light Detection and Ranging (LIDAR) system, mayuse time-of-flight (TOF)-based measurement circuit 110 and a 3D imagereconstruction circuit 150 based on a signal received from an opticaldetector circuit 130 and associated optics 140, with a pulsed lightemitting device array 120 as a light source. The time-of-flightmeasurement circuit 110 may determine the distance d to target T bymeasuring the round trip (“time-of-flight”; ToF) of a laser pulse 109reflected by the target T (where d=(speed of light (c)/2)×ToF), whichmay be used by the 3D image reconstruction circuit 150 to create anaccurate 3D map of surroundings. Some advantages of LIDAR systems mayinclude long range; high accuracy; superior object detection andrecognition; higher resolution; higher sampling density of 3D pointcloud; and effectivity in diverse lighting and/or weather conditions.Applications of LIDAR systems may include ADAS (Advanced DriverAssistance Systems), autonomous vehicles, UAVs (unmanned aerialvehicles), industrial automation, robotics, biometrics, modeling,augmented and virtual reality, 3D mapping, and security. The example ofFIG. 1 illustrates a flash LIDAR system, where the pulsed light emittingdevice array 120 emits light for short durations over a relatively largearea to acquire images, in contrast with some traditional scanning LIDARtechniques (which generate image frames by raster scanning). However, itwill be understood that light emitting device arrays 120 describedherein can be used for implementations of scanning LIDAR as well.

Still referring to FIG. 1, the light emitting device array 120 mayinclude a plurality of electrically connected surface-emitting laserdiodes, such as VCSELs, and may be operated with strong single pulses atlow duty cycle or with pulse trains, typically at wavelengths outside ofthe visible spectrum. Because of sensitivity to background light and thedecrease of the signal with distance, several watts of laser power maybe used to detect a target T at a distance d of up to about 100 metersor more.

However, some conventional VCSELs may have sizes defined by dimensions(e.g., length, width, and/or diameter) of about 150 micrometers (μm) toabout 200 μm, which may impose size and/or density constraints on sensorsystems including an array of discrete VCSELs. This relatively largeVCSEL size may be dictated for use with conventional pick-and-placemachines, as well as for sufficient contact surface area for wire bondpads to provide electrical connections to the VCSEL. For example, someconventional solder ball or wire bond technology may require more thanabout 30 μm in length for the bond pad alone, while the tip used to pullthe wire bond may have an accuracy on the order of tens of micrometers.

Some embodiments described herein provide light emitting devices, suchas surface-emitting laser diodes (e.g., VCSELs), having reduceddimensions (e.g., lengths and/or widths of about 30 micrometers (μm) orless) without affecting the device performance (e.g., power output). Forexample, the aperture of the VCSEL die (which is the active region wherethe lasing takes place) may be about 10 μm to about 20 μm in diameter.The die length can be reduced to the aperture diameter plus a fewmicrons by reducing or eliminating wasted (non-active) area, and byretaining a few microns (e.g., about 4 μm to about 6 μm or less) ofcombined chip length for the anode and the cathode contacts. This mayprovide a reduction in dimensions (e.g., length and/or width) by afactor of about 10 or more (e.g., die lengths of about 15 micrometers(μm) to about 20 μm, as compared to some conventional VCELs with dielengths of about 150 μm to about 200 μm). In some embodiments, thesereduced die dimensions may allow for fabrication of emitter arraysincluding a greater density (e.g., thousands) of VCSELs or other laserdiodes.

FIGS. 2A and 2B are plan and cross-sectional views illustrating anexample surface-emitting light emitting device (shown as a verticalcavity surface emitting laser diode (VCSEL) chip or die 200, alsoreferred to herein as a VCSEL 200) in accordance with some embodimentsdescribed herein, which includes anode and cathode contacts 211, 212that are smaller than the lasing aperture 210 in at least one dimension.As shown in FIGS. 2A and 2B, the VCSEL 200 includes an active region 205with one or more quantum wells 203 for generation and emission ofcoherent light 209. The optical cavity axis 208 of the VCSEL 200 isoriented along the direction of current flow (rather than perpendicularto the current flow as in some conventional laser diodes), defining avertical cavity with a length along the direction of current flow. Thiscavity length of the active region 205 may be short compared with thelateral dimensions of the active region 205, so that the radiation 209emerges from the surface of the cavity rather than from its edge.

The active region 205 may be sandwiched between distributed Braggreflector (DBR) mirror layers (also referred to herein as Braggreflector layers or Bragg mirrors) 201 and 202 provided on a lateralconduction layer (LCL) 206. The LCL 206 may allow for improvedelectrical and/or optical characteristics (as compared to direct contactto the reflector layer 401) in some embodiments. In some embodiments, asurface of the LCL layer 206 may provide a print interface 215 includingan adhesive layer that improves adhesion with an underlying layer orsubstrate. The adhesive layer may be optically transparent to one ormore wavelength ranges and/or can be refractive-index matched to providedesired optical performance. The reflector layers 201 and 202 at theends of the cavity may be made from alternating high and low refractiveindex layers. For example, the reflector layers 201 and 202 may includealternating layers having thicknesses dl and d2 with refractive indicesn1 and n2 such that n1d1+n2d2=λ/2, to provide wavelength-selectivereflectance at the emission wavelength λ. This vertical construction mayincrease compatibility with semiconductor manufacturing equipment. Forexample, as VCSELs emit light 209 perpendicular to the active region205, tens of thousands of VCSELs can be processed simultaneously, e.g.,by using standard semiconductor wafer processing steps to define theemission area and electrical terminals of the individual VCSELs from asingle wafer.

Although described herein primarily with reference to VCSEL structures,it will be understood that embodiments described herein are not limitedto VCSELs, and the laser diode 200 may include other types of laserdiodes that are configured to emit light 209 along an optical axis 208that is oriented perpendicular to a substrate or other surface on whichthe device 200 is provided. It will also be understood that, whiledescribed herein primarily with reference to surface-emitting laserstructures, laser diodes and laser diode arrays as described herein arenot so limited, and may include edge-emitting laser structures that areconfigured to emit light along an optical axis that is oriented parallelto a substrate or other surface on which the device is provided as well,as shown in the example of FIG. 9.

The VCSEL 200 may be formed of materials that are selected to providelight emission at or over a desired wavelength range, which may beoutside of the spectrum of light that is visible to the human eye. Forexample, the VCSEL 200 may be a gallium arsenide (GaAs)-based structurein some embodiments. In particular embodiments, the active region 205may include one or more GaAs-based layers (for example, alternatingInGaAs/GaAs quantum well and barrier layers), and the Bragg mirrors 201and 202 may include GaAs and aluminum gallium arsenide(Al_(x)Ga_((1-x))As). For instance, the lower Bragg mirror 201 may be ann-type structure including alternating layers of n-AlAs/GaAs, while theupper Bragg mirror 202 may be a p-type structure including alternatinglayers of p-AlGaAs/GaAs. Although described by way of example withreference to a GaAs-based VCSEL, it will be understood that materialsand/or material compositions of the layers 201, 202, and/or 205 may betuned and/or otherwise selected to provide light emission at desiredwavelengths, for example, using shorter wavelength (e.g., GaN-based)and/or longer wavelength (e.g., InP-based) emitting materials.

In the example of FIGS. 2A and 2B, the VCSEL 200 includes a lasingaperture 210 having a dimension (illustrated as diameter D) of about 12μm, and first and second electrically conductive contact terminals(illustrated as anode contact 211 and cathode contact 212, also referredto herein as first and second contacts). A first electrically conductivefilm interconnect 213 is provided on the first contact 211, and a secondelectrically conductive film interconnect 213 is provided on the secondcontact 212 to provide electrical connections to the VCSEL 200. FIG. 2Bmore clearly illustrates the anode contact 211 and cathode contact 212in cross section, with the conductive film interconnects 213 thereon.The first and second contacts 211 and 212 may provide contacts tosemiconductor regions of opposite conductivity type (P-type and N-type,respectively). Accordingly, embodiments described herein are configuredfor transfer of electric energy to the VCSEL contacts 211 and 212through thin-film interconnects 213, which may be formed by patterningan electrically conductive film, rather than incorporating wire bonds,ribbons, cables, or leads. The interconnections 213 may be formed afterproviding the VCSEL 200 on a target substrate (e.g., a non-nativesubstrate that is different from a source substrate on which the VCSEL200 is formed), for example, using conventional photolithographytechniques, and may be constructed to have low resistance. In thisregard, materials for the electrically conductive film interconnects 213may include aluminum or aluminum alloys, gold, copper, or other metalsformed to a thickness of approximately 200 nm to approximately 500 nm.

As shown in FIG. 2A, the first and second conductive contacts 211 and212 are smaller than the aperture 210 in one or more dimensions. In someembodiments, allowing about 2 μm to about 3 μm for the dimensions ofeach of the contacts 211, 212, the overall dimensions of the VCSEL die200 can be significantly reduced. For example, for anode and cathodecontacts that are 2 μm in length each, a dimension L can be reduced toabout 16 μm (2 μm anode length+12 μm aperture+2 μm cathode length; allmeasured along dimension L) providing a 16×16 μm² die. As anotherexample, for anode and cathode contacts that are 3 μm in length each, adimension L can be reduced to about 18 μm (3 μm anode+12 μm aperture+3μm cathode) providing an 18×18 μm² die. Die dimensions L may be furtherreduced or slightly increased for smaller aperture dimensions D (e.g.,10 μm) or larger aperture dimensions D (e.g., 20 μm). More generally,VCSEL dies 200 according to some embodiments herein may achieve acontact area-to-aperture area ratio of about 0.05 to 30, about 0.1 to20, about 1 to 10, or about 1 to 3, where the contact area refers to thesurface area of electrical contacts 211 and/or 212 positioned on oradjacent the aperture 210 on the surface S. Also, although illustratedwith reference to contacts 211, 212 and interconnections 213 atparticular locations relative to the aperture 210, it will be understoodthat embodiments described herein are not so limited, and the contacts211, 212 and interconnections 213 may be provided at other areas of theVCSEL die 200 (e.g., at corners, etc.).

VCSELs 200 in accordance with some embodiments described herein may beconfigured to emit light with greater than about 100 milliwatts (mW) ofpower within about a 1-10 nanosecond (ns) wide pulse width, which may beuseful for LIDAR applications, among others. In some embodiments, morethan 1 Watt peak power output with a 1 ns pulse width at a 10,000:1 dutycycle may be achieved from a single VCSEL element 200, due for instanceto the reduced capacitance (and associated reduction in RLC timeconstants) as compared to some conventional VCSELs. VCSELs 200 asdescribed herein may thus allow for longer laser lifetime (based uponlow laser operating temperatures at high pulsed power), in combinationwith greater than about 200 meter (m) range (based on very high poweremitter and increased detector sensitivity).

FIG. 2C is a plan view illustrating the VCSEL chip 200 in accordancewith some embodiments described herein in comparison to a conventionalVCSEL chip 10. As shown in FIG. 2C, the conventional VCSEL chip 10 mayhave a length L of about 200 μm, to provide sufficient area for theactive region 5 and the top conductive wire bond pad 11, which mayfunction as an n-type or p-type contact. In contrast, VCSEL chips 200 inaccordance with some embodiments described herein may have a length L ofabout 20 μm or less. As electrical connections to the smaller contacts211, 212 are provided by thin-film metallization interconnects 213,VCSEL chips 200 in accordance with some embodiments described hereinrequire no bond pad, such that the optical aperture 210 occupies amajority of the overall surface area of the emitting surface S.

VCSEL chips 200 according to some embodiments of the present inventionmay thus have dimensions that are 1/100^(th) of those of someconventional VCSEL chips 10, allowing for up to one hundred times morepower per area of the emitting surface S, as well as reduced capacitancewhich may substantially reduce the RLC time constants associated withdriving fast pulses into these devices. Such an exponential reduction insize may allow for fabrication of VCSEL arrays including thousands ofclosely-spaced VCSELs 200, some of which are electrically connected inseries (or anode-to-cathode) on a rigid or flexible substrate, which maynot be possible for some conventional closely spaced VCSELs that arefabricated on a shared electrical substrate. For example, as describedin greater detail below, multiple dies 200 in accordance with someembodiments described herein may be assembled and electrically connectedwithin the footprint of the conventional VCSEL chip 10. In someapplications, this size reduction and elimination of the bond pad mayallow for reduction in cost (of up to one hundred times), devicecapacitance, and/or device thermal output, as compared to someconventional VCSEL arrays.

FIG. 3A is a perspective view illustrating a distributed emitter array300 a including laser diodes (illustrated as VCSELs 200) in accordancewith some embodiments described herein. The array 300 a (also referredto herein as a distributed VCSEL array (DVA)) may be assembled on anon-native substrate 307 a, for example, by micro-transfer printing,electrostatic adhesion, or other mass transfer techniques. As usedherein, a non-native substrate (also referred to herein as a targetsubstrate) may refer to a substrate on which the laser diodes 200 arearranged or placed, which differs from a native substrate on which thelaser diodes 200 are grown or otherwise formed (also referred to hereinas a source substrate). The substrate 307 a may be rigid in someembodiments, or may be flexible in other embodiments, and/or may beselected to provide improved thermal characteristics as compared to thesource substrate. For example, in some embodiments the non-nativesubstrate 307 a may be thermally conducting and also electricallyinsulating (or coated with an insulating material, such as an oxide,nitride, polymer, etc.). Electrically conductive thin-film interconnects313 may be formed to electrically connect respective contacts of thelaser diodes 200 in series and/or parallel configurations, and may besimilar to the interconnects 213 described above. This may allow fordynamically adjustable configurations, by controlling operation ofsubsets of the laser diodes 200 electrically connected by the conductivethin-film interconnects 313. In some embodiments, the array 300 a mayinclude wiring 313 between VCSELs 200 that are not connected in parallel(e.g., connections without a shared or common cathode/anode). That is,the electrically conductive thin-film interconnects 313 may providenumerous variations of series/parallel interconnections, as well asadditional circuit elements which may confer good yield (e.g. bypassroutes, fuses, etc.).

The conductive thin-film interconnects 313 may be formed in a parallelprocess, before and/or after providing the laser diodes 200 on thesubstrate 307 a. For example, the conductive thin-film interconnects 313may be formed by patterning an electrically conductive film on thesubstrate 307 a using conventional photolithography techniques, suchthat the laser diodes 200 of the array 300 are free of electricalconnections through the substrate 307 a.

Due to the small dimensions of the laser diodes 200 and the connectionsprovided by the conductive thin-film interconnects 313, a spacing orpitch between two immediately adjacent laser diodes 200 is less thanabout 500 micrometers (μm), or in some embodiments, less than about 200μm, or less than about 150 μm, or less than about 100 μm, or less thanabout 50 μm, without connections to a shared or common cathode/anode.While some monolithic arrays may provide inter-laser diode spacings ofless than about 100 μm, the laser diodes of such arrays may electricallyshare a cathode/anode and may mechanically share a rigid substrate inorder to achieve such close spacings. In contrast, laser diode arrays asdescribed herein (such as the array 300 a) can achieve spacings of lessthan about 150 μm between immediately adjacent, serially-connected laserdiodes 200 (that do not have a common anode or cathode connection), onnon-native substrates (e.g., rigid or flexible substrates) in someembodiments. In addition, as described below with reference to theexamples of FIGS. 6A-6C, some embodiments of the present disclosure mayintegrate other types of devices and/or devices formed from differentmaterials (e.g. power capacitors, FETs, etc.) in-between laser diodes200 at the sub-150 μm spacings described herein.

Also, in some embodiments, a concentration of the laser diodes 200 perarea of the array 300 a may differ at different portions of the array300 a. For example, some LIDAR sensor applications may benefit fromhigher resolution in a central portion of the array (corresponding to aforward direction of travel), but may not require such high resolutionat peripheral regions of the array. As such, a concentration of VCSELs200 at peripheral portions of the array 300 a may be less than aconcentration of VCSELs 200 at a central portion of the array 300 a insome embodiments. This configuration may be of use in applications wherethe substrate is flexible and may be curved or bent in a desired shape,as shown in FIG. 3B.

FIG. 3B is a perspective view illustrating a distributed emitter array300 b including laser diodes 200 on a curved, non-native substrate 307 bin accordance with some embodiments described herein. In someembodiments, the substrate 307 b is formed of a flexible material thatcan be bent to provide curved emitting surface, such that VCSELs 200mounted on a central portion 317 of the substrate 307 b face a forwarddirection, while VCSELs 200 mounted on peripheral portions 317′ of thesubstrate 307 b face oblique directions. As the VCSELs 200 respectivelyemit light in a direction perpendicular to their active regions, theVCSELs 200 mounted on the central portion 317 emit light 309 in theforward direction, while the VCSELs 200 mounted on peripheral portions317′ of the substrate 307 b emit light 309′ in oblique directions,providing a wide field of view. In some embodiment, each VCSEL mayprovide narrow-field illumination (e.g., covering less than about 1degree), and the arrays 300 a, 300 b may include hundreds or thousandsof VCSELs 200 (e.g., an array of 1500 VCSELs, each covering a field ofview of about 0.1 degree, can provide a 150 degree field of view).

The field of view can be tailored or changed as desired from 0 degreesup to about 180 degrees by altering the curvature of the substrate 307b. The curvature of the substrate 307 b may or may not be constantradius, and can thereby be designed or otherwise selected to provide adesired power distribution. For example, the substrate 307 b may definea cylindrical, acylindrical, spherical or aspherical curve whose normalsurfaces provide a desired distribution of relative amounts of power. Insome embodiments, the curvature of the substrate 307 b may bedynamically altered by mechanical or electro-mechanical actuation. Forexample, a mandrel can be used to form the cylindrical or acylindricalshape of the flexible non-native substrate 307 b. The mandrel can alsoserve as a heat sink in some embodiments. Also, as mentioned above, aspatial density or concentration of VCSELs 200 at peripheral portions ofthe array 300 b may be less than a concentration of VCSELs 200 at acentral portion of the array 300 b in some embodiments. For example,rows or columns of the array 300 b of VCSELs 200 may be arranged on thenon-native substrate 307 b at different and/or non-uniform pitches toprovide a desired far-field output light pattern, for instance, usingmicro-transfer printing and/or other micro-assembly techniques.

The arrays 300 a and 300 b illustrated in FIGS. 3A and 3B may bescalable based on a desired quantity or resolution of laser diodes 200,allowing for long range and high pulsed power output (on the order ofkilowatts (kW)). The spatial density or distribution of the laser diodes200 on the surfaces of the substrates 307 a and 307 b can be selected toreduce optical power density, providing both long range and eye safetyat a desired wavelength of operation (e.g., about 905 nm for GaAsVCSELs; about 1500 nm for InP VCSELs). A desired optical power densitymay be further achieved by controlling the duty cycle of the signalsapplied to the VCSELs and/or by altering the curvature of the substrate.Also, the separation or spacing between adjacent laser diodes 200 withinthe arrays 300 a and 300 b may be selected to provide thermal managementand improve heat dissipation during operation, depending on thesubstrate material. For example, a spacing between two immediatelyadjacent laser diodes 200 of greater than about 100 μm micrometers (μm)may provide thermal benefits, especially for substrates with limitedthermal conductivity. The arrays 300 a and 300 b as described herein maythereby provide greater reliability, by eliminating wire bonds,providing a fault-tolerant architecture, and/or providing loweroperating temperatures. In further embodiments, self-aligning, low-costbeam forming micro-optics (e.g., ball lens arrays) may be integrated onor into the surface of the arrays 300 a and 300 b.

The compact arrays 300 a and 300 b shown in FIGS. 3A and 3B may befabricated in some embodiments using micro-transfer printing (MTP),electrostatic adhesion, and/or other massively parallel chip handlingtechniques that allow simultaneous assembly and heterogeneousintegration of thousands of micro-scale devices on non-native substratesvia epitaxial liftoff For example, the arrays of VCSELs 200 can befabricated using micro-transfer printing processes similar to thosedescribed, for example, in U.S. Pat. No. 7,972,875 to Rogers et al.entitled “Optical Systems Fabricated By Printing-Based Assembly,” thedisclosure of which is incorporated by reference herein in its entirety.The arrays of VCSELs 200 can alternatively be fabricated usingelectrostatic adhesion or gripping transfer techniques similar to thosedescribed, for example in U.S. Pat. No. 8,789,573 to Bibl et al.entitled “Micro device transfer head heater assembly and method oftransferring a micro device,” the disclosure of which is incorporated byreference herein in its entirety. In some embodiments, MTP,electrostatic adhesion, and/or other mass transfer techniques may allowfor fabrication of VCSEL or other arrays of laser diodes with the smallinter-device spacings described herein.

FIGS. 4A-4F are perspective views and FIGS. 4A′-4G′ are cross-sectionalviews illustrating an example fabrication process for laser diodes(illustrated as VCSELs 400) in accordance with some embodimentsdescribed herein. The VCSELs 200 described herein may also be fabricatedusing one or more of the processing operations shown in FIGS. 4A-4F insome embodiments. As shown in FIGS. 4A-4F and FIGS. 4A′-4G′, ultra smallVCSELs 400 in accordance with embodiments described herein can be grownon source substrates and assembled on a non-native target substrateusing micro-transfer printing techniques. In particular, in FIG. 4A and4A′, sacrificial layer 408, a lateral conduction layer 406, a first,n-type distributed Bragg reflector (DBR) layer 401, an active region405, and a second, p-type DBR layer 402 are sequentially formed on asource wafer or substrate 404. Although illustrated with reference to asingle VCSEL 400 to show fabrication, it will be understood that aplurality of VCSELs 400 may be simultaneously fabricated on the sourcewafer 404, with reduced or minimal spacing between adjacent VCSELs 400to increase or maximize the number of VCSELs that may be simultaneouslyfabricated on the wafer 404. Also, it will be understood that aplurality of VCSEL devices may be fabricated on a single die or chipletthat is released from the substrate 404 for printing. Also, the transfertechniques described in greater detail below may allow for reuse of thesource wafer 404 for subsequent fabrication of additional VCSELs.

In some embodiments, the material compositions of the layers 406, 401,405, and 402 may be selected to provide a desired emission wavelengthand emission direction (optical axis). For example, the layers 406, 401,405, and 402 may be gallium arsenide (GaAs)-based or indium phosphide(InP)-based in some embodiments. As illustrated, a lateral conductionlayer 406, an AlGaAs n-type high-reflectivity distributed Braggreflector (DBR), and an active region 405 are sequentially formed on thesource wafer 404. The active region 405 may be formed to includeInAlGaAs strained quantum wells designed to provide light emission overa desired wavelength, and is followed by formation of a p-type DBRoutput mirror 402. A top contact metallization process is performed toform a p-contact (e.g., an anode contact) 411 on the p-type DBR layer402. For example, Ti/Pt/Au ring contacts of different dimensions may bedeposited to form the anode or p-contact 411. An aperture 410 may bedefined within a perimeter of the p-contact 411. In some embodiments, anoxide layer may be provided between the active region 405 and the p-typeDBR layer 402 to define boundaries of the aperture 410. The placementand design of the aperture 410 may be selected to minimize opticallosses and current spreading.

In FIG. 4B and 4B′, a top mesa etching process is performed to exposethe active region 405 and a top surface of the n-type DBR layer 401, andan oxidation process is performed to oxidize the exposed surfaces,(including the exposed sidewalls of the active region 405), and inparticular to laterally define boundaries of the optical aperture 410.In FIG. 4C and 4C′, a bottom contact metallization process is performedto expose and form an n-type (e.g., cathode) contact 412 on a surface ofthe lateral conduction layer 406. It will be understood that, in someembodiments, the n-type contact 412 may alternatively be formed on then-type DBR layer 401 to provide the top-side contact. In FIG. 4D and4D′, an isolation process is performed to define respective lateralconduction layers 406, and an anchor material (e.g., photoresist layer)is deposited and etched to define photoresist anchors 499 and inlets toexpose sacrificial release layer 408 for epitaxial lift-off.

In FIG. 4E and 4E′, an undercut etching process is performed to removeportions of the sacrificial release layer 408 such that the anchors 499suspend the VCSEL die 400 over the source wafer 404. In someembodiments, the operations of FIG. 4E and 4E′ may be followed by amicro-transfer printing process, as shown in FIGS. 4F and 4F′, which mayutilize an elastomeric and/or other stamp 490 to break the anchors 499,adhere the VCSEL die 400 (along with multiple other VCSEL dies 400 onthe source wafer 404) to a surface of the stamp 490, and simultaneouslytransfer the multiple VCSEL dies 400 (which have been adhered to thesurface of the stamp) to a non-native target substrate 407 by contactingthe surface of the stamp including the dies 400 thereon with a surfaceof the non-native target substrate 407, as shown in FIG. 4G′. In otherembodiments, the operations of FIG. 4F may be followed by anelectrostatic gripper-based transfer process, which may utilize anelectrostatic transfer head to adhere the VCSEL die 400 (along withmultiple other VCSEL dies 400 on the source wafer 404) to a surface ofthe head using the attraction of opposite charges, and simultaneouslytransfer the VCSEL dies 400 to a non-native target substrate. As aresult of breaking the anchors 499, each VCSEL die 400 may include abroken or fractured tether portion 499 t (e.g., a residual portion ofthe anchor structure 499) protruding from or recessed within an edge orside surface of the die 400 (and/or a corresponding relief feature at aperiphery of the die 400), which may remain upon transfer of the VCSELdies 400 to the non-native substrate 407.

The non-native target substrate may be a rigid or flexible destinationsubstrate for the VCSEL array, or may be a smaller interposer or“chiplet” substrate. Where the target substrate is the destinationsubstrate for the array, an interconnection process may form aconductive thin film layer on the target substrate including theassembled VCSEL dies 400 thereon, and may pattern the conductive thinfilm layer to define thin-film metal interconnects that provide desiredelectrical connections between the VCSEL dies 400. The interconnectionprocess may be performed after the VCSEL dies 400 are assembled on thedestination substrate, or may be performed in a pre-patterning processon the destination substrate before the VCSEL dies 400 are assembledsuch that the electrical connections between the VCSEL dies 400 arerealized upon assembly (with no interconnection processing requiredafter the transfer of the dies 400 onto the substrate). Where the targetsubstrate is a chiplet, the VCSEL dies 400 may be connected in parallelvia the chiplet. The chiplets including the VCSEL dies 400 thereon maythen be assembled (via transfer printing, electrostatic adhesion, orother transfer process) onto a destination substrate for the array,which may be pre- or post-patterned to provide electrical connectionsbetween the chiplets. The thin-film metal interconnects may be definedon and/or around the broken tether portion protruding from the edge ofthe die(s) 400 in some embodiments.

Because the VCSELs 400 are completed via epitaxial lift-off and thus areseparated from the substrate and/or because of the use of thin filminterconnects, the VCSELs 400 may also be thinner than some conventionalVCSELs which remain connected to their native substrate, such as theVCSEL 10 of FIG. 2C. For example, the VCSEL 400 may have a thickness t(e.g., a combined thickness of the semiconductor stack including thelayers 406, 401, 405, and 402) of about 1 micrometers (μm) to about 20μm.

FIGS. 5A-5C are images of VCSEL arrays 500 in accordance with someembodiments described herein, which were assembled using micro-transferprinting processes. In particular, FIG. 5A illustrates a VCSEL array 500of about 11,000 lasers with an inter-VCSEL spacing of about 200micrometers(μm) or less between adjacent VCSELs 200 after assembly on anon-native substrate 507, with the inset image of FIG. 5B and the imageof FIG. 5C illustrating a magnified views of portions of the array 500including about 350 lasers and 9 lasers, respectively, in accordancewith some embodiments described herein. Due to the reduction indimensions of the VCSELs described herein, the inter-VCSEL spacingbetween immediately adjacent VCSELs 200 may be less than about 150 μm,or less than about 100 μm or less than about 50 μm on the sourcesubstrate in some embodiments. In some embodiments, the array 500 mayinclude 100 VCSELs or more within a footprint or area of 5 squaremillimeters (mm²) or less.

FIGS. 5D-5E are magnified images illustrating broken tether portions andrelief features of VCSEL structures in accordance with some embodimentsdescribed herein. As shown in FIGS. 5D and 5E, a transfer-printed VCSEL510 (such as one of the VCSELs 200) or other laser diode as describedherein may include one or more broken tether portions 499 t and/orrelief features 599 at a periphery thereof The relief features 599 maybe patterned or otherwise provided along the periphery of VCSEL 510 topartially define the tethers 499 and areas for preferential fracture ofthe tethers 499. In the examples of FIGS. 5D-5E, the broken tetherportions 499 t and relief features 599 are illustrated as being presentalong a periphery of the lateral conduction layer (LCL) 506; however, itwill be understood that broken tether portions 499 t and/or relieffeatures 599 may be present in or along a periphery of any of the layersthat may be provided on a non-native substrate by transfer-printingprocesses described herein, for example, any of the epitaxially grownlayers 406, 405, 401, 402 formed in fabricating the active region 405 ona source wafer or substrate 404 in the examples of FIGS. 4A-4F and4A′-4G′. As such, in some embodiments, the broken tether portion 499 tmay comprise a material and thickness corresponding to that of the LCLlayer 506 (or other layer associated with the active region). In furtherembodiments, to shorten an etch sequence, peripheral or edge portions ofthe LCL 506 may be partially etched, and as such, the relief pattern 599of the tether features 499 t may be thinner than the LCL 506 (or otherlayer associated with the active region). The fracture of the tethers499 during the “Pick” operation (such as shown in FIG. 4G′) may occur inthe resist layer 499l itself, and the broken tether portions 499 t maycomprise a material and thickness corresponding to that of the resistlayer 499l. The broken tether portion 499 t may interact with the printadhesive or epoxy, and also remains on the fully processed device, evenafter resist develop and/or resist removal processes. More generally,some laser diode structures in accordance with embodiments describedherein may include at least one of a broken tether portion 499 t or arelief pattern or feature 599 at areas adjacent the tethers 499 along aperiphery or edge of the laser diode structure.

Accordingly, some embodiments described herein may use MTP to print andintegrate hundreds or thousands of VCSELs or other surface-emittinglaser diodes into small-footprint light-emitting arrays. MTP may beadvantageous by allowing simultaneous manipulation and wafer-levelassembly of thousands of laser diode devices. In some embodiments, eachof the laser diodes may have aperture dimensions as small as about 1-10μm, thereby reducing the size (and cost) of lasers incorporating suchVCSEL arrays by a factor of up to 100. Other embodiments may includesubstrates with aperture dimensions even smaller than about 1 μm inorder to realize different performance such as modified near and farfield patterns. Still other embodiments may use larger apertures, forexample, about 10-100 μm, in order to realize higher power output perVCSEL device. Also, MTP allows reuse of the source wafer (e.g., GaAs orInP) for growth of new devices after the transfer printing process,further reducing fabrication costs (in some instances, by up to 50%).MTP may also allow heterogeneous integration and interconnection oflaser diodes of different material systems (e.g., GaAs or InP lasers)and/or driver transistors (as discussed below) directly onto siliconintegrated circuits (ICs). Also, source wafers may be used and reused ina cost-effective manner, to fabricate laser diodes (e.g., InP-basedVCSELs) that can provide high power with eye safety, as well as reducedambient noise. As such, MTP may be used in some embodiments to reduceemitter costs, and allow fabrication of high power, high resolutiondistributed VCSEL arrays (DVAs) including multiple hundreds or thousandsof VCSELs.

Also, when provided on flexible or curved substrates, embodimentsdescribed herein can provide DVAs having a wide field of view (FoV), upto 180 degrees horizontal. In some embodiments, the optical powerdispersed via the DVA can be configured for eye safety and efficientheat dissipation. In some embodiments, low-cost, self-aligning, beamforming micro-optics may be integrated within the curved DVA.

FIG. 6A is a perspective view illustrating an example emitter array 600including heterogeneous integration of distributed surface-emittinglaser diodes (illustrated as VCSELs 200) and distributed drivertransistors 610 in accordance with some embodiments described herein. Asused herein, distributed circuit elements may refer to laser diodes,driver transistors, and/or other circuit elements that are assembled invarious desired positions throughout a laser diode array, and such anarray of distributed circuit elements is referred to herein as adistributed array. In some embodiments, the distributed array may be atwo-dimensional array including rows and columns. For example,integration of distributed high power driver transistors in adistributed VCSEL array may be advantageous for LIDAR applications. FIG.6B is schematic view illustrating an equivalent circuit diagram for thedistributed emitter array 600 of FIG. 6A, and FIG. 6C is across-sectional view of the distributed emitter array 600 taken alongline 6C-6C′ of FIG. 6A.

As shown in FIGS. 6A-6C, the array 600 (also referred to herein as aDVA) may be assembled on a non-native substrate 607, for example, bymicro-transfer printing or other techniques. The substrate 607 may berigid in some embodiments, or may be flexible in other embodiments. Thearray 600 further includes integrated driver transistors 610 that areassembled on the substrate 607 adjacent to one or more of the VCSELs200. For example, the driver transistors 610 may be assembled on thesubstrate 607 using a micro-transfer printing (MTP) process. In someembodiments, an array including hundreds or thousands of drivertransistors 610 may be provided. Electrically conductive thin-filminterconnects 613 may be formed to electrically connect respectivecontacts of the driver transistors 610 and laser diodes 200 in seriesand/or parallel configurations. Spacings between a driver transistor 610and an immediately adjacent laser diode 200 may be less than about 2millimeters, less than about 1 millimeter, less than about 500micrometers, less than about 150 micrometers (μm), or in someembodiments, less than about 100 μm, or less than about 50 μm, which mayprovide reduced parasitic impedance therebetween (e.g., up to 100 timeslower than where the driver transistor 610 is located off-chip oroff-substrate).

In some embodiments, the array 600 may include wiring 613 between VCSELs200 that are not connected in parallel (e.g., no common cathode/anode).Interconnection designs that do not simply place all elements of thearray in parallel (e.g., without a common anode or cathode connection)may offer the advantage of lowering current requirements for the array,which can reduce inductive losses and increase switching speed. Variedinterconnection designs also provide for the inclusion of other devicesembedded or integrated within the electrically interconnected array(e.g., switches, gates, FETs, capacitors, etc.) as well as structureswhich enable fault tolerance in the manufacture of the array (e.g.fuses, bypass circuits, etc.) and thus confer yield advantages. Forexample, as illustrated in FIG. 6B, the array 600 includes a pluralityof strings of VCSELs 200 that are electrically connected in series (oranode-to-cathode) to define columns (or other subsets or sub-arrays) ofthe array 600. The array 600 further includes an array of drivertransistors 610, with each driver 610 electrically connected in serieswith a respective string of serially-connected (or otherwiseanode-to-cathode-connected) VCSELs 200.

The conductive thin-film interconnects 613 may be formed in a parallelprocess after providing the laser diodes 200 and driver transistors 610on the substrate 607, for example by patterning an electricallyconductive film using conventional photolithography techniques. As such,the driver transistors 610 and laser diodes 200 of the array 600 arefree of wire bonds and/or electrical connections through the substrate607. Due to the smaller dimensions of the laser diodes 200 and thedriver transistors 610 and the degree of accuracy of the assemblytechniques described herein, a spacing between immediately adjacentlaser diodes 200 and/or driver transistors 610 may be less than about150 micrometers (μm), or in some embodiments, less than about 100 μm orless than about 50 μm. Integrating the driver transistors 610 on thesubstrate 607 in close proximity to the VCSELs 200 (for example, atdistances less than about 2 millimeters, less than about 1 millimeter,less than about 500 micrometers, less than about 150 micrometers (μm),or in some embodiments, less than about 100 μm, or less than about 50 μmfrom a nearest VCSEL 200) may thus shorten the electrical connections613 between elements, thereby reducing parasitic resistance, inductance,and capacitance (e.g., a parasitic impedance), and allowing for fasterswitching response. In some embodiments, the use of processes such as,for example, micro-transfer printing, electrostatic adhesion, or othermass transfer techniques, may allow for the arrangement of VCSELs 200and driver transistors 610 that may otherwise be process-incompatible(e.g., made by different processes that may utilize operations and/ormaterials that are otherwise difficult to integrate). In a conventionalsystem not using such procedures, equivalent driver electronics may beplaced further away and/or off-chip from the emitter structures at leastin part due to the different processes that are used to construct them.In some embodiments as described herein, however, the driver transistors610 and VCSELs 200 may be placed in closer proximity. Thus, though theydriver transistors 610 and VCSELs 200 may be placed as close as 150 μm,benefits over conventional devices may be achieved even at furtherdistances, including 5 mm, 2 mm, and/or 1 mm. Devices constructedaccording to some embodiments described herein may have a parasiticimpedance that is less than one hundred times that of a conventionaldevice, allowing for much more rapid switching capabilities.

In the example of FIGS. 6A-6C, the driver transistors 610 are arrangedin an array such that each driver transistor 610 is connected in serieswith a column (or other subset) of serially-connected (or otherwiseanode-to-cathode-connected) VCSELs 200, allowing for individual controlof respective columns/strings of VCSELs 200. However, it will beunderstood that embodiments described herein are not limited to such aconnection configuration. To the contrary, integrating the drivertransistors 610 in close proximity to the VCSELs 200 may also allow forgreater flexibility in wiring configurations (e.g., in series and/orparallel), which may be used to control current and/or increase ormaximize performance. For example, fewer or more driver transistors 610may be provided (e.g., drivers for control of rows of serially-connectedVCSELs 200 as well as columns) for finer control of respective VCSELs orgroups of VCSELs and/or output power. Another example would be theaddition of capacitors or similar electrical storage devices close tothe elements of the array for faster pulse generation, for example, onthe order of sub-nanosecond (ns), in contrast to some conventionaldesigns that may be on the order of about 1-10 ns or more. Likewise,although illustrated as a planar array 600, the substrate 607 may beflexible in some embodiments; thus, the array 600 may be bent to providea desired curvature, similar to the array 300 b of FIG. 3B.

As similarly discussed above with reference to the arrays 300 a and 300b, the array 600 may be scalable based on a desired quantity orresolution of laser diodes 200, allowing for long range and high pulsedpower output (on the order of kilowatts (kW)). The distribution of thelaser diodes 200 on the surfaces of the substrate 607 can be selectedand/or the operation of the laser diodes can be dynamically adjusted orotherwise controlled (via the transistors 610) to reduce optical powerdensity, providing both long range and eye safety at a desiredwavelength of operation (e.g., about 905 nm for GaAs VCSELs; about 1500nm for InP VCSELs). Also, the spacing between elements 200 and/or 610may be selected to provide thermal management and improve heatdissipation during operation. Arrays 600 as described herein may therebyprovide improved reliability, by eliminating wire bonds, providing afault-tolerant architecture, and/or providing lower operatingtemperatures. In further embodiments, self-aligning, low-cost beamforming micro-optics (e.g., ball lens arrays) may be integrated on orinto the surface of the substrate 607.

FIG. 6D is a schematic view illustrating an equivalent circuit diagramof the distributed emitter array 600 of FIG. 6A in which the emitters200 are individually addressable. As illustrated in FIG. 6D, the array600 includes a plurality of strings of VCSELs 200 that are electricallyconnected in series (or anode-to-cathode) to define columns (or othersubsets or sub-arrays) of the array 600. The array 600 further includesan array of driver transistors 610, with each driver transistor 610electrically connected in series with a respective string ofserially-connected VCSELs 200. The driver transistors 610 may beindividually addressable via column signals COLUMN. In some embodiments,the driver transistors 610 may be individually activated (e.g., biasedso as to be conducting) so as to vary power provided to a respectivestring of the serially-connected VCSELs 200. In some embodiments, thedriver transistors 610 may be operated in linear mode so as to vary aresistance of the driver transistor 610 and accordingly vary a currentapplied to the string of serially-connected VCSELs 200.

Rows of the array 600 may also be individually addressable. For example,the array 600 may utilize bypass circuits to individually select one ofthe rows of the string of serially connected VCSELs 200. In someembodiments, individual bypass transistors 628 may be utilized to selectrespective ones of the VCSELs 200. For example, to select a particularVCSEL 200 at a particular row and column, the driver transistor 610 forthe string containing the particular VCSEL 200 may be activated toprovide current through the string, and the bypass transistor 628associated with the particular VCSEL 200 may be turned off (e.g., biasedso as to be non-conducting) so that current through the string may flowthrough the VCSEL 200. In some embodiments, the bypass transistor 628may be operated in linear mode to provide a variable resistance alongthe bypass path. The variable resistance may allow for control of theamount of current flowing through the VCSEL 200.

The circuit embodiment of FIG. 6D is merely an example of how the arrayof emitters 600 may be configured to be both row and column addressable.However, the embodiments described herein are not limited to thisparticular arrangement. One of ordinary skill in the art will recognizethat other potential circuit arrangements are possible to implement anactive matrix of devices that may be selectively addressed by both rowand column, for example, to direct a larger fraction of pulse energy tosome subset of the VCSELs in order to modify the far field pattern ofthe emitted output beam, such that only certain directions are receivinga greater amount of power. Such circuit arrangements may be used insteadof the circuit arrangement of FIG. 6D without deviating from the scopeof the embodiments described herein.

FIG. 7A is a perspective view illustrating a LIDAR device 700 aincluding surface-emitting laser diodes (such as the VCSELs 200) inaccordance with embodiments described herein, illustrated relative to apencil for scale. FIG. 7C is a perspective view illustrating analternative LIDAR device 700 c in accordance with embodiments describedherein. In particular, FIGS. 7A and 7C illustrate a distributedvertical-cavity-surface-emitting laser (VCSEL) array-based, solid-stateFlash LIDAR device 700 a, 700 c. The LIDAR device 700 a, 700 c isillustrated with reference to a curved array 720, such as the curvedarray 300 b of FIG. 3B, but it will be understood that the LIDAR device700 a, 700 c is not so limited, and may alternatively implement thearray 300 a of FIG. 3A, the array 600 of FIGS. 6A-6C, and/or otherarrays of laser diodes 200 that provide features described herein. Suchfeatures of the device 700 a, 700 c may include, but are not limited to,broad field of view (in particular embodiments, about θ=120° horizontalby ϕ=10° vertical, or broader); long range (in some instances, greaterthan about 200 m); high resolution (in particular embodiments, about0.1° horizontal and vertical) compact size defined by reduced dimensions(in particular embodiments, about 110×40×40 mm); high power (inparticular embodiments, about 10,000w peak, pulsed); and eye safety (inparticular embodiments, dispersed optical power can support eye safe,high power, 905 nm (e.g., GaAs) and/or about 1500 nm (e.g., InP)emitters).

FIG. 7B is an exploded view 700 b illustrating components of the LIDARdevice 700 a of FIG. 7A. As shown in FIG. 7B, the device housing orenclosure 701 includes a connector 702 for electrical connection to apower source and/or other external devices. The enclosure 701 is sizedto house a light emitter array 720, a light detector array 730,electronic circuitry 760, detector optics 740 (which may include one ormore lenses and/or optical filters), and a lens holder 770. Atransparent cover 780 is provided to protect the emitter array 720 anddetector optics 740, and may include beam shaping and/or filteringoptics in some embodiments.

The light emitter array 720 may be a pulsed laser array, such as any ofthe VCSEL arrays 300 a, 300 b, 600 described herein. As such, the lightemitter array 720 may include a large quantity (e.g., hundreds or eventhousands) of distributed, ultra small laser diodes 200, which arecollectively configured to provide very high levels of power (byexploiting benefits of the large number of very small devices). Using alarge number of small devices rather than a small number of largedevices allows devices that are very fast, low power and that operate ata low temperature to be integrated in an optimal configuration (withother devices, such as transistors, capacitors, etc.) to provideperformance not as easily obtained by a small number of larger laserdevices. As described herein the laser diodes 200 may be transferprinted simultaneously onto a non-native curved or flexible substrate insome embodiments. Beam shaping optics that are configured to projecthigh aspect ratio illumination from the light emitter array 720 onto atarget plane may also be provided on or adjacent the light emitter array720.

The light detector array 730 may include one or more optical detectordevices, such as pin, pinFET, linear avalanche photodiode (APD), siliconphotomultiplier (SiPM), and/or single photon avalanche diode (SPAD)devices, which are formed from materials or otherwise configured todetect the light emitted by the light emitter array 720. The lightdetector array 730 may include a quantity of optical detector devicesthat are sufficient to achieve a desired sensitivity, fill factor, andresolution. In some embodiments, the light detector array 730 may befabricated using micro-transfer printing processes as described herein.The detector optics 740 may be configured to collect high aspect ratioecho and focus target images onto focal plane of the light detectorarray 730, and may be held on or adjacent the light detector array 730by the lens holder 770.

The electronic circuitry 760 integrates the above and other componentsto provide multiple return LIDAR point cloud data to data analysis. Moreparticularly, the electronic circuitry 760 is configured to controloperation of the light emitter array 720 and the light detector array730 to output filtered, high-quality data, such as 3D point cloud data,to one or more external devices via the connector 702. The externaldevices may be configured to exploit proprietary and/or open source 3Dpoint cloud ecosystem and object classification libraries for analysisof the data provided by the LIDAR device 700 a, 700 c. For example, suchexternal devices may include devices configured for applicationsincluding but not limited to autonomous vehicles, ADAS, UAVs, industrialautomation, robotics, biometrics, modeling, augmented and virtualreality, 3D mapping, and/or security.

FIG. 8 is a block diagram illustrating an example system 800 for a LIDARdevice, such as the LIDAR device 700 a, 700 b, 700 c of FIGS. 7A-7C, inaccordance with some embodiments described herein. As shown in FIG. 8,the system 800 integrates multiple electrically coupled integratedcircuit elements to provide the LIDAR device functionality describedherein. In particular, the system 800 includes a processor 805 that iscoupled to a memory device 810, an illumination circuit 820, and adetection circuit 830. The memory device 810 stores computer readableprogram code therein, which, when executed by the processor, operatesthe illumination circuit 820 and the detection circuit 830 to collect,process, and output data, such as 3D point cloud data, indicative of oneor more targets in the operating environment. The system 800 may furtherinclude a thermistor 842 and associated temperature compensation circuit843, as well as a power management circuit 841 that is configured toregulate voltage or power to the system 800.

The illumination circuit 820 includes an array of discretesurface-emitting laser diodes 200, driver transistor(s) 610, andassociated circuit elements 611, electrically connected in any ofvarious configurations. In some embodiments, the illumination circuit820 may be a laser array including rows and/or columns of VCSELs 200,such as any of the VCSEL arrays 300 a, 300 b, 600 described herein.Operation of the illumination circuit 820 to emit light pulses 809 maybe controlled by the processor 805 via a modulation and timing circuit815 to generate a pulsed light output 809. Beam-shaping and/or focusingoptics may also be included in or adjacent the array of laser diodes 200to shape and/or direct the light pulses 809.

The detection circuit 830 may include a time-of-flight (ToF) detector851 coupled to a ToF controller 852. The ToF detector 851 may includeone or more optical detector devices, such as an array of discrete pin,pinFET, linear avalanche photodiode (APD), silicon photomultiplier(SiPM), and/or single photon avalanche diode (SPAD) devices. The ToFcontroller 852 may determine the distance to a target by measuring theround trip (“time-of-flight”) of a laser pulse 809′ reflected by thetarget and received at the ToF detector 851. In some embodiments, thereflected laser pulse 809′ may be filtered by an optical filter 840,such as a bandpass filter, prior to detection by the ToF detector 851.The output of the detection block 830 may be processed to suppressambient light, and then provided to the processor 805, which may performfurther processing and/or filtering (via signal processor discriminatorfilter 817, and may provide the filtered output data (for example, 3Dpoint cloud data) for data analysis. The data analysis may include framefiltering and/or image processing. In some embodiments, the dataanalysis may be performed by an external device, for example, anautonomous vehicle intelligence system.

FIG. 9 is a cross-sectional view illustrating an example laser diodearray 900 including edge-emitting laser diodes 910 in accordance withfurther embodiments described herein. As shown in FIG. 9, a laser diode910 includes an active region 905 (which may include one or more quantumwells) for generation and emission of coherent light 909. The activeregion 905 is provided between p-type and n-type layers 901 and 902,with contacts 912 and 911 thereon, respectively. A diffraction gratinglayer may be included to provide feedback for lasing. The optical cavityaxis of the laser diode 910 is oriented perpendicular to the directionof current flow, defining an edge-emitting device, so that the radiation909 emerges from the edge of the device 910 rather than from a topsurface thereof. The devices 910 may be assembled on a non-nativesubstrate 907, for example, by micro-transfer printing, electrostaticadhesion, or other mass transfer techniques. Respective mirror elements(illustrated as micro-steering mirrors 913) may also be assembled on thesubstrate 907 (for example, by micro-transfer printing, electrostaticadhesion, or other mass transfer techniques), and oriented relative tothe optical cavity axis of a laser diode 910 that is to be providedadjacent thereto, such that the radiation 909 from the laser diode 910is reflected and ultimately emitted in a direction perpendicular to thesubstrate 907.

The substrate 907 may be rigid in some embodiments, or may be flexiblein other embodiments, and electrically conductive thin-filminterconnects may be formed to electrically connect respective contactsof the laser diodes 910 in series and/or parallel configurations, atspacings similar to those described with reference to the arrays 300 a,300 b, and/or 600 herein. Likewise, as described above with reference tothe examples of FIGS. 6A-6C, the array 900 may include other types ofdevices and/or devices formed from different materials (e.g., powercapacitors, FETs, micro-lens arrays, etc.) integrated with the laserdiodes 910 on the substrate 907 at the spacings described herein.

The VCSEL arrays described herein may be advantageously used withexisting TOF devices, such as existing detector arrays utilizing pin,pinFET, linear APD, SiPM, and/or SPAD devices. In some embodiments, theMTP techniques described herein may additionally be utilized inmanufacturing photo detectors (also referred to herein as “detectors”)and/or photo detector arrays. FIGS. 10A and 10B are cross-sectionalviews of examples of a detector 1000 having reduced dimensions inaccordance with some embodiments described herein. The detector 1000 maybe fabricated using micro-transfer printing, electrostatic adhesion, orother mass transfer techniques.

Referring to FIG. 10A, the detector 1000 may include a first epitaxiallayer 1001 and a second epitaxial layer 1005. In some embodiments, thefirst epitaxial layer 1001 may be a p− layer and the second epitaxiallayer 1005 may be an n− epitaxial layer. The first epitaxial layer 1001may include a buried layer 1009. In some embodiments, the buried layer1009 may be a p buried layer. The second epitaxial layer 1005 mayinclude well regions 1003. In some embodiments, the well regions 1003may be p-type well regions. The well regions 1003 may additionallyinclude first contact layers 1009. In some embodiments, the firstcontact layers 1009 may be p+contact layers. The second epitaxial layer1005 may further include a second contact layer 1006. In someembodiments, the second contact layer 1006 may be an n+ layer. The firstcontact layers 1009 may be connected to anode 1011, and the secondcontact layer 1006 may be connected to cathode 1018. Electricalinterconnects 1012 may be connected to anode 1011 and cathode 1018respectively. The electrical interconnects 1012 may be isolated from thevarious layers of the detector 1000 by insulating layer 1014, though, insome embodiments, the insulating layer 1014 may be optional. Though thedescription herein highlights some conductivity types and associatedconcentrations for the detector 1000 of FIG. 10A, it will be understoodthat other configurations are possible without deviation from the spiritand scope of the embodiments discussed herein.

The detector 1000 is configured to detect incident light 1019 strikingthe detector 1000 and generate an electrical signal based on thedetected light. In some embodiments, by adjusting a biasing voltageapplied to the anode 1011 and/or cathode 1018, a sensitivity of thedetector 1000 may be adjusted. In other words, by altering a biasing ofthe detector 1000, the response of the detector 1000 to the incidentlight 1019 may be adjusted, thereby making the system level sensitivityor output of the detector 1000 adjustable.

The detector 1000 may be formed on a source wafer and placed on anon-native substrate 1007 in a manner similar to that described withrespect to FIGS. 4A-4F and 4A′-4H′. In some embodiments, the detector1000 may be individually placed as a discrete device. For example, thedetector 1000 may be formed to have a tether 1017 that may beselectively broken such that the detector 1000 may be transferred to thenon-native substrate 1007. For example, a stamp may be used to breakanchor structures to release the detector 1000 from a source wafer,adhere the detector 1000 to a surface of the stamp, and simultaneouslytransfer the multiple detector 1000 to the non-native substrate 1007 bycontacting the surface of the stamp including the detectors 1000 thereonwith the non-native substrate 1007, defining print interfaces 1015therebetween. In some embodiments, the print interface 1015 between thedetector 1000 and the non-native substrate 1007 may include an adhesivelayer. As a result of the MTP processing, tether artifacts 1017 mayremain as part of the detector 1000. For example, the detector 1000 mayexhibit tethers and/or relief features such as those described hereinwith respect to the VCSEL 200 (e.g., FIGS. 5D and 5E).

Embodiments described herein may allow for the formation of detectors1000 that have a reduced individual dimension. For example, as part ofan MTP process, the detector 1000 may be printed directly on thenon-native substrate 1007. In some embodiments, the detector 1000 may beprinted on supporting circuitry to realize an array of detectors 1000having sizes defined by dimensions (e.g., length, width, and/ordiameter) of about 100 micrometers (μm) to about 200 μm. In someembodiments, the dimensions are about 4 to about 40 μm. In someembodiments, the dimensions are about 30 μm. In some embodiments, thedetectors may be spaced apart from one another by less than 150 μm, butthe embodiments described herein are not limited thereto. In someembodiments, the detectors may be spaced apart from one another by lessthan 20 μm. In some embodiments, the detectors may be spaced apart fromone another by less than 5 μm. In some embodiments, the detectors may bespaced apart from one another by less than 2 μm.

Referring to FIG. 10B, the detector 1000 may be disposed, as part of theMTP processing, on other circuit layers. For example, a logic layer 1021may be between the detector 1000 and the substrate 1007. The logic layer1021 may contain additional circuitry, such as support circuitry (e.g.,additional detector logic) for the detector 1000. In some embodiments,the logic layer 1021 may contain ToF support circuits such as ToFprocessing circuits and/or ToF timing control circuits. The detector1000 may be formed on the logic layer 1021 using the micro-transferprinting techniques. For example, a stamp may be used to break anchorstructures to release the detector 1000 from a source wafer, adhere thedetector 1000 to a surface of the stamp, and simultaneously transfer themultiple detector 1000 to respective logic layers 1021 by contacting thesurface of the stamp including the detectors 1000 thereon withrespective surfaces of the logic layers 1021, defining print interfaces1015 therebetween. In some embodiments, the print interface 1015 betweenthe detector 1000 and the logic layer 1021 may include an adhesivelayer.

Though particular configurations of detector 1000 are illustrated inFIGS. 10A and 10B, it will be understood that other configurations arepossible. For example, alternate configurations based on knownimplementations of photo detectors may be used, such as those based onpin, pinFET, linear APD, SiPM, electron-injection and/or SPAD devices.In some embodiments, the detector 1000 may be GaN-based, GaAs-basedand/or InP-based, though the embodiments described herein are notlimited thereto.

FIG. 11A illustrates an example of a conventional detector array. Asillustrated in FIG. 11A, a conventional detector structure 1150 mayinclude an integrated detector and additional elements (e.g., logic,memory, a ring oscillator, etc.). However, the size of the integrateddetector may be relatively small as compared to the size of theconventional detector structure 1150. In some conventional arrangements,the fill factor (e.g., the ratio of the area of the integrated detectorto the area of the conventional detector structure 1150) may be as lowas 20%.

FIG. 11B illustrates an example of a detector array 1070 and individualdetector 1000, according to some embodiments described herein. Incontrast to the conventional arrangement of FIG. 11A, detectors 1000printed using an MTP process, electrostatic adhesion, or other masstransfer technique may result in the ability to arrange the detectors1000 on the supporting logic circuit (illustrated in dashed lines) forthe detectors 1000 to create a detector structure 1080. For example, theelectrical circuits for elements supporting the detector 1000 (e.g.,logic, memory, etc.) may be formed first on a source substrate, and thedetector 1000 may be printed using the MTP process on an upper surfaceof the electrical circuits to create a detector structure 1080. As aresult, a fill factor (e.g., the ratio of the surface area of thedetector 1000 to the surface area of the detector structure 1080) for adetector structure 1080 utilizing an MTP process as described herein mayapproach 80% or more. In some embodiments, the fill factor may begreater than or equal to 90%. By using the individual detectors 1000with the increased fill factor, the detectors 1000 may be arranged in anarray 1070 that occupies less area than a conventional array.

FIG. 11C illustrates a schematic representation of a distributed array1070 of detectors 1000 printed on a non-native substrate 1007, accordingto some embodiments described herein. As illustrated in FIG. 11C, thedetectors 1000 may be arranged in a row-column architecture. In someembodiments, the individual detectors 1000 may be separatelyaddressable, as discussed with respect to FIGS. 6B and 6D. In otherwords, control elements may be added to allow for the individualaddressability of individual detectors 1000 of the detector array 1070.

As discussed herein with respect to FIGS. 6A-6D, the respectivedetectors 1000 may be connected with conductive thin-film interconnects.Due to the small dimensions of the detectors 1000 and the connectionsprovided by the conductive thin-film interconnects, a spacing betweentwo immediately adjacent detectors 1000 may be less than about 150micrometers (μm). In some embodiments, the spacing between twoimmediately adjacent detectors 1000 may be less than 5 μm, or in someembodiments, less than about 20 μm, or less than about 30 μm. Inaddition, as described herein with reference to the examples of FIGS.6A-6D, some embodiments of the present disclosure may integrate othertypes of devices and/or devices formed from different materials (e.g.power capacitors, FETs, etc.) in-between detectors 1000 at the sub-150μm spacings described herein.

In some embodiments, MTP, electrostatic adhesion, or other mass transferprocessing may be used to arrange individual detectors 1000 andindividual VCSELs 200 on a common substrate. FIG. 12A illustrates aschematic representation of a combination of VCSELs 200 and detectors1000 heterogeneously integrated on a non-native substrate 1007,according to some embodiments described herein. As illustrated in FIG.12A, a plurality of VCSELs 200 may be arranged adjacent a plurality ofdetectors 1000. For convenience of illustration, only representativeimages are provided for the VCSELs 200 and detectors 1000. However, itwill be understood that the VCSELs 200 may be provided in an array of Mrows by N columns, where M and N are integers of 1 or greater.Similarly, the detectors 1000 may be provided in R rows by S columns,where R and S are integers of 1 or greater. In some embodiments, M maybe equal to R and/or N may be equal to S, but the embodiments describedherein are not limited thereto. In some embodiments, M may be differentthan R, and N may be different than S.

As previously described, use of the MTP, electrostatic adhesion, orother mass transfer process allows for the placement of the VCSELs 200and detectors 1000 on the non-native substrate 1007 in series orparallel configurations, and the forming of electrical interconnectsbetween the various devices, such as the thin-film electricalinterconnects 613 of FIG. 6A. The non-native substrate 1007 may be rigidor flexible, and may include integrated driver transistors, such asintegrated driver transistors discussed with respect to FIGS. 6A-6D. Thearrangement of the VCSELs 200 adjacent the detectors 1000 allows forboth devices to be commonly provided on a single substrate. Given thereduced size of both the VCSELs 200 and the detectors 1000, theembodiments described herein provide a dense distributed array capableof supporting both the emission and detection of laser signals.

Though FIG. 12A illustrates a configuration in which an array of VCSELs200 is adjacent an array of detectors 1000, it will be understood thatother configurations are available. For example, FIGS. 12B and 12Cillustrate example configurations in which arrays of VCSELs 200 anddetectors 1000 are variously arranged, according to some embodimentsdescribed herein. FIG. 12B illustrates a configuration in which a singlearray of VCSELs 200 is flanked on both sides by arrays of detectors1000. FIG. 12C illustrates a configuration including multiple arrays ofboth VCSELs 200 and detectors 1000. In some embodiments, a spatialdensity or concentration of one or more of the arrays of detectors 1000may differ from other ones of the arrays of detectors 1000. For example,spatial density or concentration of detectors 1000 at peripheralportions of the non-native substrate 1007 may be less than aconcentration of VCSELs 200 at a central portion of the non-nativesubstrate 1007. Having reduced detection capability at peripheralportions of the non-native substrate 1007 may provide a lowerresolution, and a subsequent lower power consumption, at peripheralportions of the field of view where higher detail may not be necessary.It will be understood by those of skill in the art that otherconfigurations of VCSELs 200 and detectors 1000 are possible utilizingthe MTP process without deviating from the embodiments described herein.

FIGS. 13A and 13B illustrate examples of heterogeneous configurations ofemitters 200 and detectors 1000 on a non-native substrate 1007,according to some embodiments described herein. In some embodiments, theemitters 200 may be VCSEL emitters as described herein. As illustratedin FIG. 13A, emitters 200 and detectors 1000 may be arranged on a sameside of the non-native substrate 1007. Individual emitters 200 may emitlight in a direction that extends away from the non-native substrate1007. In some embodiments, the emitters 200 may emit light substantiallyperpendicular to the surface of the non-native substrate 1007, but theembodiments described herein are not so limited. For example, in someembodiments, the emitters 200 may be mounted at an angle to thenon-native substrate 1007. In some embodiments, the emitters 200 may beedge-emitting laser structures.

The detectors 1000 may be mounted on a same side of the non-nativesubstrate 1007 as the emitters 200. In some embodiments, both theemitters 200 and the detectors 1000 may be mounted to the same side ofthe non-native substrate 1007 via an MTP process as described herein.The detectors 1000 may detect incident light that is directed towardsthe surface of the non-native substrate 1007. The detectors 1000 may beconfigured to detect reflections of the laser light emitted by emitters200 so as to form a data representation of the environment illuminatedby the laser light emitted by the emitters 200. The arrangement of theemitters 200 and detectors 1000 in FIG. 13A are intended as examples,and the embodiments described herein are not limited to the particulararrangement illustrated in FIG. 13A.

FIG. 13B illustrates an example in which the emitters 200 and thedetectors 1000 are mounted on opposites sides of the non-nativesubstrate 1007′. In some embodiments, the non-native substrate 1007′ maybe transparent with respect to at least the emission wavelengths of thelight output from the emitters 200. The emitters 200 may be configuredto emit laser light through the non-native substrate 1007′. For example,the emitters 200 may be VCSEL emitters such as the one illustrated inFIG. 2B, and the emitter 200 may be mounted so that the aperture of theemitter 200 faces the non-native substrate 1007′. Similarly, the emitter200 could be an edge-emitting laser structure such as the oneillustrated in FIG. 9, and the mirrors (see FIG. 9) may be arranged soas to reflect emitted light through the non-native substrate 1007′.

The detectors 1000 may be mounted on the opposite side of the non-nativesubstrate 1007′ as the emitters 200. In some embodiments, both theemitters 200 and the detectors 1000 may be mounted to opposite sides ofthe non-native substrate 1007′ via an MTP process as described herein.The detectors 1000 may detect incident light that is direct towards thesurface of the non-native substrate 1007 in a similar manner asdescribed with respect to FIG. 13A. In some embodiments, the emitters200 may be arranged so as to emit light through portions of thenon-native substrate 1007 that are not occupied by detectors 1000 orother circuit elements. In other words, the emitters 200 may be placedso as to radiate laser light through portions of the non-nativesubstrate 1007 in which the laser light will not be impeded by otherstructures on the non-native substrate 1007.

By placing at least some of the emitters 200 and detectors 1000 onopposite sides of the non-native substrate 1007′, the overall size ofthe heterogeneous array of emitters 200 and detectors 1000 may bereduced. In addition, placing at least some of the emitters 200 anddetectors 1000 on opposite sides of the non-native substrate 1007 mayimprove thermal performance of the heterogeneous array of emitters 200and detectors 1000 by increasing the distance between adjacent elements(e.g., emitters 200 and/or detectors 1000). The arrangement of theemitters 200 and detectors 1000 in FIG. 13A are intended as examples,and the embodiments described herein are not limited to the particulararrangement illustrated in FIG. 13B.

Referring back to FIG. 2B, VCSELs 200 may be implemented using longwavelength materials (e.g., which emit light over a wavelength range ofabout 1100 nm to about 1600 nm or more) for the active region 205. Insome embodiments, the VCSELs 200 may be implemented using shortwavelength materials (e.g., which emit light over a wavelength range ofabout 350 nm to about 450 nm, or less) for the active region 205. Insome embodiments, VCSELs 200 implemented using short wavelengthmaterials maybe combined in a distributed array with VCSELs 200implemented using long wavelength materials. That is, a heterogeneousarray may include multiple laser diodes 200, 200′ that emit light indifferent wavelength ranges.

For example, in LIDAR applications, intensity data from multiple lasershaving different emission wavelengths may allow for improveddifferentiation of materials, based for instance on differences intarget reflectance for the different wavelengths. However, fabricatingarrays including lasers of different emission wavelengths may involvechallenges. For example, the physical length (and thus, the optical pathlength as a function of the physical length and the refractive index) ofthe optical cavity may be different for lasers of different emissionwavelengths. For a VCSEL 200 configured to emit shorter-wavelengthlight, the DBR layers 201, 202 may be selected for the shorterwavelength active regions 205 (e.g., GaN). For a VCSEL 200 configured toemit longer wavelength light, the materials of the DBR layers 201, 202may be selected for the longer wavelength active regions 205 (e.g.,InP). Mechanisms for constructing VCSELs 200 of different wavelengthsare discussed in co-pending U.S. patent application Ser. No. 15/951,727entitled “Emitter Structures for Ultra-Small Vertical Cavity SurfaceEmitting Lasers (VCSELs) and Arrays Incorporating the Same,” the entirecontents of which are incorporated herein by reference.

FIGS. 14A-14D illustrate arrays in which emitters and detectors ofdifferent wavelengths may be combined in heterogeneous arrays, accordingto some embodiments described herein. As shown in the perspective viewof FIG. 14A, laser diodes 200 and 200′ that emit light in differentwavelength ranges may be heterogeneously-interspersed on a substrate1007 in the same array 1210 a. Additionally or alternatively, laserdiodes 200 and 200′ that emit light in different wavelength ranges maybe assembled in respective sections or areas 1195 and 1295 of the samearray 1210 b, as shown in the perspective view of FIG. 14B. That is,multi-wavelength laser diode arrays 1210 a, 1210 b in accordance withembodiments described herein may include multiple lasers of differentwavelengths that are homogeneously arranged in respective sectionsand/or heterogeneously interspersed throughout one or more sections ofan array substrate 1007. Also, in some embodiments, a concentration ofthe laser diodes 200 and/or 200′ per area of the arrays 1210 a, 1210 bmay differ at different sections of the array, for example, as maybenefit some LIDAR sensor applications that provide higher resolution(via a greater concentration of laser diodes 200 and/or 200′) in acentral portion of the array corresponding to a forward direction oftravel, but lower resolution (via a lesser concentration of laser diodes200 and/or 200′) at peripheral regions of the array. Additionally oralternatively, the curvature of the substrate 1007 may be configured toprovide a desired power distribution; for example, the substrate 1007may define a cylindrical, acylindrical, spherical or aspherical curvewhose normal surfaces provide a desired distribution of relative amountsof power. In some embodiments, the curvature of the substrate 1007 maybe dynamically altered, in a manner similar as discussed above withreference to the substrate 307 b of FIG. 3B.

The arrays 1210 a, 1210 b illustrated by way of example in FIGS. 14A and14B may include hundreds or thousands of closely-spaced VCSELs 200,200′, some of which may be electrically connected in series or inparallel configurations. For example, multiple VCSELs 200, 200′, inaccordance with some embodiments described herein, may be assembled andelectrically connected in series within the footprint of theconventional VCSEL chip 10 of FIG. 2C. Electrically conductive thin-filminterconnects may be formed to electrically connect respective contactsof the VCSELs 200, 200′ in series and/or parallel configurations, andmay be similar to the interconnects 213 described above. The conductivethin-film interconnects may be formed in a parallel process, before,after, or between fabrication of one or more sublayers of the laserdiodes 200, 200′ on the substrate 1007, for instance, by patterning anelectrically conductive film using conventional photolithographytechniques. The laser diodes 200, 200′ may thus be free of electricalconnections through the substrate 1007. Due to the small dimensions ofthe laser diodes 200, 200′ and the connections provided by theconductive thin-film interconnects, a spacing between two immediatelyadjacent laser diodes 200, 200′ may be less than about 150 micrometers(μm), or in some embodiments, less than about 100 μm, or less than about50 μm, without connections to a shared or common cathode/anode.

The VCSELs 200, 200′ may further integrate devices and/or devices formedfrom different materials (e.g. power capacitors, FETs, etc.) in-betweenVCSELs 200, 200′ at the sub-150 μm spacings described herein, forexample, in a manner similar to the arrangements described above withreference to the distributed array 600 and driver transistors 610 ofFIGS. 6A-6D. Likewise, the VCSELs 200, 200′ and/or sublayers thereof maybe fabricated using any of the techniques described above with referenceto FIGS. 4A-4F and 4A′-4H′. More generally, the fabrication techniques,device integration, and/or non-native substrate characteristicsdescribed herein with reference to particular laser diode structures(and/or sublayers thereof) may be used to fabricate any of the laserdiode structures, sublayers thereof, and/or laser arrays describedherein.

In some embodiments, the detectors 1000 described herein may beconfigured to detect light emitted from laser diodes 200, 200′ havingmultiple wavelengths. Thus, in some embodiments, the detector 1000described herein may be combined in heterogeneous arrays with laserdiodes 200 and/or 200′. In some embodiments, a detector 1000′ may beconfigured to detect particular wavelengths. FIG. 14C illustrates adetector 1000′ which has been configured to detect only or primarilylight of a particular wavelength. The detector 1000′ of FIG. 14C mayoperate similarly to the detector 1000 of FIG. 10, and descriptions ofduplicate portions are omitted for brevity. In the detector 1000′ tunedfor a particular wavelength, a filter 1425 may be added to be on and, insome embodiments cover, portions of the detector 1000′ that areconfigured to detect emitted light. In some embodiments, the filter 1425may be applied to the detector 1000′ via an MTP process. In someembodiments, a particular detector 1000′ may be configured to detect aparticular wavelength of emitted light from a particular emitter 200,200′. As illustrated in FIG. 14D, an array of detectors 1000 configuredto detect light of multiple wavelengths and/or detectors 1000′configured to detect light of a particular wavelength, may be combined,along with VCSELs 200, 200′ in an array on a substrate 1007. In someembodiments, as discussed herein, an MTP process may be used to arrangethe VCSELs 200, 200′ and the detectors 1000, 1000′ on the substrate 1007to create the heterogeneous array.

FIGS. 15A-15C illustrate examples of configurations of detectors 1000that provide a wider field of view, according to some embodimentsdescribed herein. As illustrated in FIG. 15A, a lenslet 1510 may beprovided on a detector 1000. The lenslet 1510 may allow for incidentlight 1019 to be concentrated into focused light 1019′ that may bedetected by the detector 1000. In a conventional configuration withoutthe lenslet 1510, the amount of incident light 1019 detected by thedetector 1000 may be a function of the location of that detector 1000 onthe substrate 1007. The detector 1000 may be limited to detectingincident light 1019 that arrives that within a particular range ofangles relative to a line normal to an upper surface of the detector1000. For example, the detector 1000 may be capable of detectingincident light 1019 that is within 45 degrees of a line normal to theupper surface of the detector 1000 (e.g., an angle of incidence of 45degrees). Thus, the detector 1000 may have difficulty detecting, or beunable to detect, incident light 1019 that arrives at greater angles. Inother words, the detector 1000 may have a limited field of view (FOV).

Adding the lenslet 1510 may allow for the FOV of the detector 1000 to beincreased. The lenslet 1510 may concentrate incident light 1019 arrivingat a greater angle of incidence, and provide the focused incident light1019′ to the detector 1000 at a smaller angle of incidence. Thus, theFOV of the detector 1000 may be increased. By increasing the FOV, thedetector 1000 may be able to collect light from a broader range. Forexample, in a LIDAR system, this may mean an increased width ofdetection in front of the LIDAR system. In some embodiments, the lenslet1510 may be printed on the detector 1000 via an MTP process. In someembodiments, the lenslet 1510 may be formed of a glass lens element, asilicone-on-glass lens element, and/or other materials that aretransparent at least to the incident light 1019.

Though FIG. 15A illustrates a unitary lenslet 1510 on the detector 1000,it will be understood that other configurations are possible. Forexample, as illustrated in FIG. 15B, a lenslet 1510′ may be provided tocover a plurality of detectors 1000. FIG. 15C illustrates anotherconfiguration of a lenslet 1510″ that may cover a plurality of detectors1000. In the embodiment of FIG. 15C, individual lenslet features 1520have been provided within the lenslet 1510″. The lenslet 1510″ with theindividual lenslet features 1520 may allow for a wider FOV with equaldistribution of the incident light 1019 across all, or many, of theindividual detectors 1000. In some embodiments, the lenslet features1520 may be defined in the surface of the lenslet 1510″ by a molding,casting, embossing, and/or etching process.

FIGS. 16A and 16B illustrate an integrated system-on-chip (SoC) 1600incorporating the heterogeneous array of emitters and detectors,according to some embodiments described herein. As illustrated in FIG.16A, the integrated SoC 1600 may be configured to provide ToF and/ordetection functionality to an electronic device 1650. In someembodiments, the electronic device 1650 may be phone and/or camera. Theintegrated SoC 1600 may be configured to provide a complete solutionthat may be quickly and easily integrated into an existing electronicdevice 1650 to provide scanning and/or LIDAR functionality.

Referring to FIG. 16A, the integrated SoC 1600 may include aheterogeneous combination of detectors 1604 and emitters 1603 commonlyprovided on a substrate 1607. The emitters 1603 may be substantially thesame as the VCSELs 200, 200′ described herein. In some embodiments, theemitters 1603 may include laser emitters having a wavelength of 905 nm.The detectors 1604 may be substantially the same as the detectors 1000,1000′ described herein. In some embodiments, the emitters 1603 and/orthe detectors 1604 may be printed on the substrate 1607 using an MTPprocess as described herein.

In some embodiments, the detectors 1604 may provided as an array behinda lens 1602. In some embodiments, the lens 1602 may be a wide-anglelens, and may include an integrated bandpass filter. The integrated SoC1600 may further include a ToF timing control processor 1610 configuredto control the emitters 1603 and detectors 1604. For example, the ToFtiming control processor 1610 may control a timing and/or power level ofthe emitters 1603. Methods of controlling a beam generated by theemitters 1603 is discussed in co-pending U.S. patent application Ser.No. 15/951,824 entitled “Devices with Ultra-Small Vertical CavitySurface Emitting Laser Emitters Incorporating Beam Steering,” the entirecontents of which are incorporated herein by reference. Methods ofshaping a beam generated by the emitters 1603 is discussed in co-pendingU.S. patent application Ser. No. 15/951,760 entitled “Beam Shaping forUltra-Small Vertical Cavity Surface Emitting Laser (VCSEL) Arrays,” theentire contents of which are incorporated herein by reference. In someembodiments, the ToF timing control processor 1610 may be configured togenerate a 3D point cloud based on the operations of the emitters 1603and detectors 1604.

The integrated SoC 1600 may further include charge storage elements1608. The charge storage elements 1608 may be configured to storecharges for driving/operating the emitters 1603 and/or detectors 1604.In some embodiments, the charge storage elements 1608 may be capacitors.The integrated SoC may further include an input/output port 1606. Theinput/output port 1606 may be configured to receive input in the form ofcontrol commands and provide output, such as to the electronic device1650. In some embodiments, the input/output port 1606 may be used toprovide a generated 3D point cloud based on the operation of theemitters 1603 and detectors 1604, though the present embodiments are notlimited thereto. In some embodiments, the input/output port 1606 may beconfigured to provide output of other portions of the integrated SoC1600, such as the detectors 1604, and the 3D point cloud may begenerated by the electronic device 1650.

In some embodiments, the integrated SoC 1600 may provide a LIDAR systemwith a range of at least ten meters. The LIDAR system provided by theSoC 1600 may have a field of view of at least sixty degrees and a poweroutput of 400 mW. The emitters 1603 and detectors 1604 of the SoC 1600may provide a resolution of 1 degree or smaller. In some embodiments,the SoC 1600 may provide a resolution of about 0.1 degrees. Because ofthe use of the MTP process, the SoC may be capable of achieving areduced form factor. In some embodiments, the form factor of the SoC1600 may be 10×10×8 mm. In some embodiments, the width and/or lengthdimensions (e.g., in a direction parallel to a surface of the substrate1607) of the SoC 1600 may be less than 2 mm.

FIG. 16B is a block diagram of an electronic apparatus 2000 capable ofimplementing the integrated SoC of FIG. 16A. The electronic apparatus2000 may use hardware, software implemented with hardware, firmware,tangible computer-readable storage media having instructions storedthereon and/or a combination thereof, and may be implemented in one ormore computer systems or other processing systems. As such, the devicesand methods described herein may be embodied in any combination ofhardware and software. In some embodiments, the electronic apparatus2000 may be part of an imaging and/or LIDAR system.

As shown in FIG. 16B, the electronic apparatus 2000 may include one ormore processors 2010 and memory 2020 coupled to an interconnect 2030.The interconnect 2030 may be an abstraction that represents any one ormore separate physical buses, point to point connections, or bothconnected by appropriate bridges, adapters, or controllers. Theinterconnect 2030, therefore, may include, for example, a system bus, aPeripheral Component Interconnect (PCI) bus or PCI-Express bus, aHyperTransport or industry standard architecture (ISA) bus, a smallcomputer system interface (SCSI) bus, a universal serial bus (USB), IIC(I2C) bus, or an Institute of Electrical and Electronics Engineers(IEEE) standard 1394 bus, also called “Firewire.”

The processor(s) 2010 may be, or may include, one or more programmablegeneral purpose or special-purpose microprocessors, digital signalprocessors (DSPs), programmable controllers, application specificintegrated circuits (ASICs), programmable logic devices (PLDs),field-programmable gate arrays (FPGAs), trusted platform modules (TPMs),or a combination of such or similar devices, which may be collocated ordistributed across one or more data networks. The processor(s) 2010 maybe configured to execute computer program instructions 2070 from thememory 2020 to perform some or all of the operations for one or more ofthe embodiments disclosed herein.

The electronic apparatus 2000 may also include one or more input/outputcircuits 2080 that may communicate with other electronic devices and/orone or more networks, including any conventional, public and/or private,real and/or virtual, wired and/or wireless network, including theInternet. The input/output circuits 2080 may include a communicationinterface and may be used to transfer information in the form of signalsbetween the electronic apparatus 2000 and another electronic device. Theinput/output circuits 2080 may include a serial interface, a parallelinterface, a network interface (such as an Ethernet card), a wirelessinterface, a radio interface, a communications port, a PCMCIA slot andcard, or the like. These components may be conventional components, suchas those used in many conventional computing devices, and theirfunctionality, with respect to conventional operations, is generallyknown to those skilled in the art. In some embodiments, the input/outputcircuits 2080 may be used to transmit and/or receive data associatedwith the embodiments described herein.

The electronic apparatus 2000 may further include memory 2020 which maycontain program code 2070 configured to execute operations associatedwith the embodiments described herein. The memory 2020 may includeremovable and/or fixed non-volatile memory devices (such as but notlimited to a hard disk drive, flash memory, and/or like devices that maystore computer program instructions and data on computer-readablemedia), volatile memory devices (such as but not limited to randomaccess memory), as well as virtual storage (such as but not limited to aRAM disk). The memory 2020 may also include systems and/or devices usedfor storage of the electronic apparatus 2000.

The electronic device 2000 may also include a ToF array 2050. The ToFarray 2050 may incorporate a heterogeneous array of individuallyaddressable emitters and/or detectors. For example, the ToF array 2050may include VCSELs such as the VCSELs 200, 200′ and detectors 1000,1000′ discussed herein. The ToF array 2050 may be in communication withthe processor(s) 2010 via the interconnect 2030. Thus, the processor(s)2010 may be able to control the ToF array 2050 through execution of thecode 2070 from the memory 2020.

The present invention has been described above with reference to theaccompanying drawings, in which embodiments of the invention are shown.However, this invention should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout.

It will be understood that when an element is referred to as being “on,”“connected,” or “coupled” to another element, it can be directly on,connected, or coupled to the other element, or intervening elements maybe present. In contrast, when an element is referred to as being“directly on,” “directly connected,” or “directly coupled” to anotherelement, there are no intervening elements present.

It will also be understood that, although the terms first, second, etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The exemplary term“lower,” can therefore, encompasses both an orientation of “lower” and“upper,” depending of the particular orientation of the figure.Similarly, if the device in one of the figures is turned over, elementsdescribed as “below” or “beneath” other elements would then be oriented“above” the other elements. The exemplary terms “below” or “beneath”can, therefore, encompass both an orientation of above and below.

The terminology used in the description of the invention herein is forthe purpose of describing particular embodiments only and is notintended to be limiting of the invention. As used in the description ofthe invention and the appended claims, the singular forms “a,” “an,” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will also be understood that theterm “and/or” as used herein refers to and encompasses any and allpossible combinations of one or more of the associated listed items. Itwill be further understood that the terms “include,” “including,”“comprises,” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Embodiments of the invention are described herein with reference toillustrations that are schematic illustrations of idealized embodiments(and intermediate structures) of the invention. As such, variations fromthe shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,the regions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the actual shape of a region of adevice and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms used in disclosing embodiments ofthe invention, including technical and scientific terms, have the samemeaning as commonly understood by one of ordinary skill in the art towhich this invention belongs, and are not necessarily limited to thespecific definitions known at the time of the present invention beingdescribed. Accordingly, these terms can include equivalent terms thatare created after such time. It will be further understood that terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe present specification and in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein. All publications, patent applications,patents, and other references mentioned herein are incorporated byreference in their entireties.

Many different embodiments have been disclosed herein, in connectionwith the above description and the drawings. It will be understood thatit would be unduly repetitious and obfuscating to literally describe andillustrate every combination and subcombination of these embodiments.Accordingly, the present specification, including the drawings, shall beconstrued to constitute a complete written description of allcombinations and subcombinations of the embodiments of the presentinvention described herein, and of the manner and process of making andusing them, and shall support claims to any such combination orsubcombination.

Although the invention has been described herein with reference tovarious embodiments, it will be appreciated that further variations andmodifications may be made within the scope and spirit of the principlesof the invention. Although specific terms are employed, they are used ina generic and descriptive sense only and not for purposes of limitation,the scope of embodiments of the present invention being set forth in thefollowing claims.

1. A semiconductor device comprising: a detector structure, wherein thedetector structure comprises: an integrated circuit on a substrate; anda photo detector on an upper surface of the integrated circuit that isopposite the substrate, wherein the substrate is non-native to the photodetector.